搜索资源列表
Example3
- 一个基于FPGA的计数器的小程序，定义时钟、异步复位、同步使能信号，计算结果。-An FPGA-based counter applet, define the clock, asynchronous reset, synchronous enable signal, the calculation results.
Example4
- 一款基于FPGA的数码显示译码器的小程序，定义动态扫描时钟信号，定义四位输入信号，检测时钟上升沿，计数器dount累加。-An FPGA-based digital display decoder small program, define dynamic scan clock signal, the definition of four input signals, detects the rising edge of the clock, the counter dount accumula
Example7
- 一个基于FPGA的步长可变加减计数器的小程序，时钟输入，增、减控制信号，转换结果。-An FPGA-based variable step-down counter applet, a clock input, add, subtract control signal, the conversion result.
TimeOutCounter
- 用于FPGA内部计数辅助DDR操作，便于开发-TimeOut Counter
Johnson_counter
- 基于FPGA的Jhonson计数器，能用按键控制流水灯-FPGA-based Jhonson counter, can control buttons light water
kaoshi
- FPGA -计数器，29减法计数器。使用verilog hdl编写格式，cyclone I 系列EP1C3TC144芯片。-FPGA programming using 29 down counter, using verilog hdl written format, cyclone I series EP1C3TC144 chips.
fp24_prj
- 这是我利用Verilog编写的一个时钟计数器，包括了时钟分钟和秒，结构简单，功能细化，而且我也将仿真结果放在该压缩文件中，通过下载到FPGA的板子当中就可以实现计数，希望对初学FPGA的同学有帮助-This is what I use Verilog prepared a clock counter, including the clock minutes and seconds, simple structure, function refinement, and I will also be
4BIT_COUNTER
- 4-bit counter which counts from 0 to 16. This logic has got one PLL needs to be regenerated based on the FPGA vendor.
LED_Counter
- this code show how to use Altium to coding LED Counter on FPGA-CPLD
a
- 基于fpga的vhdl十进制 计数器，简单好用-Decimal counter vhdl fpga-based, easy to use
clk_1024
- 基于FPGA的工程文件，是一个10位计数器的源码，适合分频使用-FPGA-based project file, is a 10-bit counter source for crossover use
counter_16
- 基于ISE14.7开发的模16的计数器，使用的FPGA开发板为Spartan 3E Start Kit-Based on the development of mold counter ISE14.7 16, FPGA development board used for the Spartan 3E Start Kit
cnt60
- 60秒加一计数器，实现0到59秒计时。可以参照此例编写一个FPGA时钟，代码用VHDL编写。开发环境为quertues ii9.1.-60 seconds with a counter, to achieve 0 to 59 seconds. Can refer to this case to write a FPGA clock, the code written in VHDL. Development environment for quertues ii9.1.
CNT4_S
- 该程序为运用VHDL语言，基于FPGA平台实现的一个四进制的计数器。-The program for the use of VHDL language, FPGA-based platforms to achieve a quaternary counter.
LPM_ROM
- 该程序是一个正弦信号发生器，信号的频率可控，利用FPGA的ROM，可以对正弦信号的相应电位进行查表，具体电位的地址由计数器得到。-The program is a sinusoidal signal generator, the frequency of the signal controlled by the FPGA ROM, may be a sinusoidal signal corresponding to the potential of the table, the address
counter_johnson
- 基于FPGA,CPLD嵌入式系统的Verilog语言，用于实现Johnson计数器。-base on the FPGA or DPLD，to complement the Johnson counter.
codes
- 5 simple verilog codes: Arithmetic.v - arithmetic operations on verilog Accumulator.v - 8 bit adder accumulator counterfpga.v - 4 bit up counter w/ fpga code UpDown3.v - 4 bit Up-down counter w/fpga code pattefier.v - pattern/sequence ident
displayCounter2.tar
- Verilog example of a program that uses a 7 segment display (included in fpga) to display a counter 0 to 99. Implemmented in FPGA Nexys3-Verilog example of a program that uses a 7 segment display (included in fpga) to display a counter 0 to 99. Imple
counter1
- 附件包括两个内容1.基于FPGA原理图设计的十进制计数器的ISE工程2.指导书一份。采用的软件平台是ISE13.3，硬件平台是Spartan-3E。-Appendix includes two contents of 1 based on the decimal counter FPGA schematic design of the ISE project a 2 guide book. The software platform is ISE13.3, the hardware platfo
digital_clk
- VHDL Code for a digital bit clock counter and 7 segment display clock on a altera DE2 board with a cyclone II FPGA